pentium ? processor compatible clock synthesizer/drive r CY2254A rev 1.0, november 25, 2006 page 1 of 7 2200 laurelwood road, santa clara, ca 95054 tel: (408) 855-0555 fax:(408) 855-0550 www.spectralinear.com y 2254a features ? multiple clock outputs to meet requirements of most pentium ? motherboards ? four pin-selectable cpu clocks @ 66.66 mhz, 60.0 mhz, and 50.0 mhz for support of intel triton ? pciset based pc ? 55.0 mhz pin-selectable cpu clock also available ( 2 option only) ? six pci clocks at 1/2 cpu clock frequency ? one i/o clock @ 24 mhz ? one keyboard controller clock @ 12 mhz ( 1 option) or one universal serial bus clock @ 48 mhz ( 2 option) ? two ref. clocks @ 14.318 mhz ? ref. 14.318 mhz xtal oscillator input cpu clock jitter < 200 ps cycle-to-cycle low skew outputs ?< 250 ps between cpu clocks ?< 250 ps between pci clocks ?< 500 ps between cpu and pci clocks ( 2 option) ? cpu clock leads pci clock by +1 ns min. to +4 ns max. ( 1 option) freq. stability = 0.01% (max.) output duty cycle 45% min. to 55% max. test mode support ( 1 option only) 3.3v or 5.0v operation internal pull-up resistors on s0, s1, and oe inputs functional description the CY2254A is a clock synthesizer/driver that provides the multiple clocks required for a pentium-based pc. the CY2254A has low-skew outputs (< 250 ps between the cpu clocks, < 250 ps between the pci clocks). in addition, the CY2254A cpu clock outputs have less than 200 ps cycle-to-cycle jitter. finally, both the pci and cpu clock outputs meet the 1 v/ns slew rate requirement of a pentium processor-based system. the CY2254A accepts a 14.318 mhz reference signal as its input. the CY2254A has 2 plls, one of which generates the cpu and pci clocks, and the other generates the i/o and keyboard controller or usb clocks. the CY2254A runs off either a 3.3v or 5v supply. the CY2254A is available in two options. the 1 option supports the intel triton pciset and provides a 12 mhz keyboard clock on pin 25. the 2 option provides a 48 mhz usb clock on pin 25 and supports the cyrix ? m1 processor. pin configuration logic block diagram xtalout xtalin ref0 (14.318 mhz) 14.318 mhz osc. 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 24 23 22 21 13 14 25 28 27 26 top view v dd xtalin xtalout v ss oe cpuclk0 cpuclk1 v dd cpuclk2 cpuclk3 v ss s1 s0 v dd ref0 ref1 v dd seebelow ioclk v ss pciclk2 pciclk3 v dd pciclk4 pciclk5 v ss pciclk1 pciclk0 ref1 (14.318 mhz) ioclk (24 mhz) cpuclk0 cpuclk1 cpuclk2 cpuclk3 pciclk0 sys pll cpu pll rom s0 s1 oe y 2 delay pciclk1 pciclk2 pciclk3 pciclk4 pciclk5 soic usbclk (48 mhz) kbdclk (12 mhz) y 2 y 2 1 2 option pin 25 kbdclk 12 mhz usbclk 48 mhz 1 option only
CY2254A rev 1.0, november 25, 2006 page 2 of 7 pin summary name 1 2 description v dd 1 1 voltage supply xtalin [1] 2 2 reference crystal input xtalout [1] 3 3 reference crystal feedback v ss 4 4 ground oe 5 5 output enable, active high (internal pull-up resistor to v dd ) cpuclk0 6 6 cpu clock output cpuclk1 7 7 cpu clock output v dd 8 8 voltage supply cpuclk2 9 9 cpu clock output cpuclk3 10 10 cpu clock output v ss 11 11 ground s1 12 12 cpu clock select input, bit 1 (internal pull-up resistor to v dd ) s0 13 13 cpu clock select input, bit 0 (internal pull-up resistor to v dd ) v dd 14 14 voltage supply pciclk0 15 15 pci clock output pciclk1 16 16 pci clock output v ss 17 17 ground pciclk5 18 18 pci clock output pciclk4 19 19 pci clock output v dd 20 20 voltage supply pciclk3 21 21 pci clock output pciclk2 22 22 pci clock output v ss 23 23 ground ioclk 24 24 i/o clock output (24 mhz) kbdclk 25 keyboard controller clock output (12 mhz) usbclk 25 universal serial bus clock output (48 mhz) v dd 26 26 voltage supply ref1 27 27 reference clock output (14.318 mhz) ref0 28 28 reference clock output (14.318 mhz) function table option oe s0 s1 xtalin cpuclk pciclk ref. clock output ioclk kbdclk 1 only usbclk 2 only 1, 2 0 x x 14.318 mhz high-z high-z high-z high-z high-z high-z 1, 2 1 0 0 14.318 mhz 50.0 mhz 25.0 mhz 14.318 mhz 24 mhz 12 mhz 48 mhz 1, 2 1 0 1 14.318 mhz 60.0 mhz 30.0 mhz 14.318 mhz 24 mhz 12 mhz 48 mhz 1, 2 1 1 0 14.318 mhz 66.66 mhz 33.33 mhz 14.318 mhz 24 mhz 12 mhz 48 mhz 1 1 1 1 tclk [2] tclk/2 tclk/4 tclk tclk/4 tclk/8 2 1 1 1 14.318 mhz 55.0 mhz 27.5 mhz 14.318 mhz 24 mhz 48 mhz note: 1. for best accuracy, use a parallel-resonant crystal, c load = 17 pf. 2. tclk is a test clock on xtalin (pin 2) during test mode.
CY2254A rev 1.0, november 25, 2006 page 3 of 7 pci clock driver strength requirements matched impedances on both rising and falling edges on the output drivers output impedance: 25 : (typical) measured at 1.5v maximum output impedance: 40 : measured at 1.5v cpu clock driver strength requirements matched impedances on both rising and falling edges on the output drivers output impedance: 25 : (typical) measured at 1.5v maximum output impedance: 40 : measured at 1.5v maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage 0.5 to +7.0v input voltage 0.5v to v dd + 0.5 storage temperature (non-condensing) 65 q c to +150 q c junction temperature............................................... +150 q c package power dissipation..... ................. .............. .......... 1w static discharge voltage............................................ >2000v (per mil-std-883, method 3015) operating conditions [3] parameter description min. max. unit v dd supply voltage 3.3v supply voltage 5.0v 3.135 4.5 3.6 5.5 v v t a operating ambient temperature 0 70 q c c l max. capacitive load on cpuclk pciclk ioclk kbdclk / usbclk ref0 ref1 20 30 20 20 30 15 pf f (ref) reference frequency, oscillator nominal value 14.318 14.318 mhz t pu power-up time for all vdd's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics v dd = 3.135v 3.6v, or 5.0v r 10%, t a = 0 q c to +70 q c parameter description test conditions min. max. unit v ih high-level input voltage except crystal inputs 2.0 v v il low-level input voltage except crystal inputs 0.8 v v oh [4] high-level output voltage v dd = v dd min. i oh = 6 ma cpuclk 2.4 v i oh = 12 ma pciclk, ref0 i oh = 4 ma kbdclk, usbclk i oh = 8 ma ref1 v ol [4] low-level output voltage v dd = v dd min. i ol = 6 ma cpuclk 0.4 v i ol = 12 ma pciclk, ref0 i ol = 4 ma kbdclk, usbclk i ol = 8 ma ref1 i ih input high current v ih = v dd, v dd = 3.3v 5 p a v ih = v dd, v dd = 5.0v 10 p a i il input low current v il = 0 v, v dd = 3.3v 100 p a v il = 0 v, v dd = 5.0v 250 p a i oz output leakage current three-state 10 +10 p a i dd power supply current v dd = 3.6v, v in = 0 or v dd v dd = 5.5v, v in = 0 or v dd 90 150 ma ma
CY2254A rev 1.0, november 25, 2006 page 4 of 7 note: 3. electrical parameters are guaranteed with these operating conditions. 4. guaranteed by design, not tested. electrical characteristics v dd = 3.135v 3.6v, or 5.0v r 10%, t a = 0 q c to +70 q c (continued) parameter description test conditions min. max. unit switching characteristics [5] parameter output name description min. max. unit t 1 all output duty cycle [6] t 1 = t 1a y t 1b 45% 55% t 2 [4] cpuclk, pciclk output rising and falling edge rate measured between 0.4 and 2.4v 1 v/ns t 3 [4] ref, kbdclk, usbclk rise time measured between 0.4 and 2.4v 4 ns t 4 [4] ref, kbdclk, usbclk fall time measured between 2.4 and 0.4v 4 ns t 5 [4] cpuclk cpu-cpu clock skew measured at 1.5v 250 ps t 6 [4] pciclk pci-pci clock skew measured at 1.5v 250 ps t 7 [4] cpuclk, pciclk cpu-pci skew measured at 1.5v ( 1 option) 1 4 ns measured at 1.5v ( 2 option) 500 ps t 8 [4] cpuclk cycle-cycle clock jitter cpu clock jitter 200 ps switching waveforms duty cycle timing t 1b t 1a 1.5v 1.5v 1.5v all outputs rise/fall time output t 2 t 3 3.3v 0v 0.4v 2.4v 2.4v 0.4v t 2 t 4
CY2254A rev 1.0, november 25, 2006 page 5 of 7 note: 5. all parameters specified with outputs fully loaded. 6. duty cycle is measured at 1.5v. switching waveforms (continued) clock skew cpuclk/ pciclk 1.5v 1.5v t 5 t 6
CY2254A rev 1.0, november 25, 2006 page 6 of 7 switching waveforms (continued) cpu-pci clock skew cpuclk 1.5v 1.5v t 7 pciclk test circuit 1 4 26 8 0.1 p f 11 14 0.1 p f v dd v dd c load outputs 17 20 23 0.1 p f 0.1 p f note: all capacitors should be placed as close to each pin as possible. 0.1 p f
rev 1.0, november 25, 2006 page 7 of 7 CY2254A while sli has reviewed all information herein for accuracy and reliability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear inc., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. ordering information ordering code package name package type operating range CY2254Asc 1 s21 28-pin soic commercial CY2254Asc 2 s21 28-pin soic commercial package drawing and dimensions 28-lead (300-mil) molded soic s21
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